Static Random-Access Memory (SRAM) sub-arrays used in System-on-Chip (SOC) products, such as those contained in handheld devices, may be implemented using dual voltage rails to achieve a reduction in area as well as stand-by power usage. In a dual voltage rail SRAM implementation, bit cells, sense-amplifiers, and pre-charge circuitries may usually be placed on a higher voltage supply rail, e.g., 1.0V-1.05V, while interface logic may be placed on a variable voltage supply rail operating at a lower operating voltage, e.g., 0.7V-0.75V.
A disadvantage of dual voltage rail SRAM implementations, however, may be a lack of dynamic power scaling during a pre-charge phase of bit lines of SRAM memory cells. In some cases, dynamic power scaling (for example, to reduce the amount of power usage) for a memory cache, e.g., a Level-2 or L2 cache, may be acceptable due to relatively lower activity and lower rates of parallel accesses. However, dynamic power scaling may not be acceptable for an SOC in a handheld product. For example, during high usage conditions, such as during a video playback mode, multiple devices and/or processes that have extensive usage of parallel SRAM for graphics generation, video encoder/decoder components, and camera units may be active. Thus, in SOCs in tablets and smart phones, 40-50 SRAM sub-arrays might be accessed simultaneously. Such high rates of parallel access can cause a significant increase in the demand for both an average and peak power for an SRAM voltage supply rail due to the full pre-charging of bit lines to the higher voltage supply rail during access operations.